This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-298506, filed Sep. 27, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device. More specifically, the present invention relates to a techniques used in a leakage test for a semiconductor memory device such as a flash EEPROM (Electrically Erasable and Programmable Read Only Memory).
2. Description of the Related Art
In recent years, microcomputer systems embedded flash memory have been used. The flash memory embedded into a microcomputer operates in sync with the system clock that controls the microcomputer system.
The memory sense circuit system of a conventional clock-synchronous flash memory will be described using FIG. 1, which is a block diagram of that flash memory.
As shown, the flash memory, indicated at 200, includes a read control circuit CNTROL1, a level control circuit LVLGEN, a read column decoder RDCOLDEC, a write column decoder WRCOLDEC, a column decoder COLDEC, a row decoder ROWDEC, an erase control circuit CNTROL2, and 32 memory blocks BLK.
The read control circuit CNTROL1 is responsive to a system clock CLK, an address select signal ROMCS and an output enable signal OE, which are supplied from the CPU in the microcomputer, to output a precharge signal PRCV, a data latch clock signal ACT2, and an output control signal CSRD. The arrangement of the read control circuit CNTROL1 is illustrated in FIG. 2A. As shown, the read control circuit CONTROL1 comprises two NAND gates 300-1 and 300-2, two buffers 310-1 and 310-2, and two inverters 320-1 and 320-2. The NAND gate 300-1 performs a logical NAND operation on the address select signal ROMCS and the system clock CLK. The NAND gate 300-2 performs a logical NAND operation on the address select signal ROMCS and the inverse of the system clock CLK from the inverter 320-1. The precharge signal PRCV is the buffered signal of the output of the NAND gate 300-1 from the buffer 310-1. The data latch clock signal ACT2 is the inverse of the output signal of the NAND gate 300-2 from the inverter 320-2. The output control signal CSRD is the buffered signal of the output enable signal OE from the buffer 310-2.
The level control circuit LVLGEN is responsive to the control signal PSV to produce a level control signal LVLDWN.
The read column decoder RDCOLDEC is responsive to address signals A3 and A2 and a read signal RD to make a selection from four read column select lines SR0 to SR3.
The write column decoder WRCOLDEC is responsive to address signals A3, A2 and a write signal WR to make a selection from four write column select lines SWR0 to SWR3.
The column decoder COLDEC is responsive to address signals A6 to A4 to make a selection from eight column select lines S0 to S7.
The row decoder ROWDEC is responsive to address signals A18 to A7 to make a selection from (n+1) word lines WL0 to WLn.
The erase control circuit CNTROL2 is responsive to an erase signal ERASE to produce erase signals ERSV and ERSPLS.
The memory block BLK includes a memory cell array ARRAY, a column selector CS, an erase switching circuit ERS_SLCT, a write control circuit PRGCNT, a write circuit WRITE, a read circuit READ, and a reference voltage generating circuit REF_VOL.
The memory cell array ARRAY has memory cells (flash cells) MC arrayed in a matrix form. The memory cells have their gates connected to the word lines WL0 to WLn and their sources connected together to a common source line SL, which in turn is connected to the erase switching circuit ERS_SLCT. The drains (bit lines BL) of the memory cells are connected to the column selector CS.
The erase switching circuit ERS_SLCT operates based on the erase signals ERSV and ERSPLS from the erase control circuit CONTROL2 and drives the source line to a high potential at the time of erasing memory cells and to ground potential otherwise.
The column selector CS is responsive to signals on the column select lines S0 to S7 to select one of the bit lines BL.
The write circuit WRITE has a write control circuit PRGCNT, a write transistor 210, and a number of select transistors 220. The write control circuit PRGCNT is responsive to a write signal WR from the CPU and write data carried to a data bus DBUS to output a write control signal PD. The transistor 210 is a pMOS transistor having its gate supplied with the write control signal PD and its source connected to a high-potential voltage source. Though only one is shown, the select transistors 220 have their gates connected to the write column select lines SWR0 to SWR3, their sources connected to the drain of the write transistor 210 and their drains connected to bit lines BL selected by the column selector CS. At write operation, a potential corresponding to write data is applied to a bit line BL selected by the column selector CS and the select transistor 220.
The read circuit READ has a plurality of select transistors 230, a bias control transistor 240, a bit-line precharging transistor 250, a sense amplifier S/A, a latch circuit LD, and a buffer 260. Though only one is illustrated, the select transistors 230 have their gates connected to the column select lines SR0 to SR3 and their sources connected to bit lines BL selected by the column selector CS. The bias control transistor 240 has its gate connected to receive the level control signal LVLDWN from the level control circuit LVLGEN and its source connected to a bit line selected by the select transistors 230 (the drains of the transistors 230). The bit line precharging transistor 250 has its gate connected to receive the precharge signal PRCV from the read control circuit CNTROL1, its source connected to a power supply and its drain connected to the drain of the bias control transistor 240 (bit line). The node between the drains of the transistors 240 and 250 is connected to an input terminal VIN of the sense amplifier S/A. The circuit arrangement of the sense amplifier S/A will be described with reference to FIG. 2B.
As shown, the sense amplifier S/A is a current mirror type of sense amplifier having two pMOS transistors 400-1 and 400-2, three nMOS transistors 410-1 to 410-3, and an inverter 420. The sense amplifier is enabled when the control signal PSV input to its enable terminal EN is asserted.
The reference voltage generating circuit REF_VOL applies a reference voltage RF to a reference voltage input terminal VREF of the sense amplifier S/A. The reference voltage generating circuit REF_VOL includes, as shown, three pMOS transistors 270-1 to 270-3 and one nMOS transistor 280. The transistor 280 is turned on when the control signal PSV is asserted, i.e., raised to a high level. As a result, a fixed reference voltage RF determined by the transistors 270-2 and 270-3 is applied to the sense amplifier S/A.
The latch circuit LD is responsive to a data latch clock signal ACT2 to hold read data VDATA output from the output terminal VOUT of the sense amplifier S/A.
The buffer 260 holds read data LDT from the latch circuit LD and responds to an output control signal CSRD output from the read control circuit CNTROL1 to output the data onto the data bus DBUS.
The read operation of the flash memory thus configured will be described next with reference to a timing diagram of FIG. 3A.
First, the CPU in the microcomputer outputs address signals A18 to A2 synchronously with the system clock CLK. The address signals identify all locations on the microcomputer including the flash memory. When the address signals are decoded and identify the flash memory 200, the address select signal ROMCS is asserted (driven to the high level). The read control circuit CNTROL1 performs a logical NAND operation on the clock CLK and the address select signal ROMCS to produce the precharge signal PRCV. Based on the address signals A6 to A2, the read column decoder RDCOLDEC selects one of the read column select lines SR0 to SR3 and the column decoder COLDEC selects one of the column select lines S0 to S7 (time t1). A bit line BL selected in this manner is charged to a precharge level during the interval when the precharge signal PRCV is asserted (dropped to a low level) and consequently the precharging transistor 250 is turned on. At time t2, the precharging of the bit line terminates. The row decoder ROWDEC selects one of the word lines WL0 to WLn based on the address signals A18 to A7 (time t2). Then, data stored in the memory cell selected by the row decoder ROWDEC and the column decoders COLDEC and RDCOLDEC is read out on to the bit line BL, changing the bit line potential. The read data on the bit line is input to the sense amplifier S/A as an input signal DT. The control signal PSV is set at a fixed potential all the time. Thus, the reference voltage generating circuit REF VOL supplies the reference potential RF to the sense amplifier S/A all the time. The sense amplifier S/A is placed in the enabled state by the control signal PSV. The sense amplifier S/A outputs an output signal VDATA, which is an amplified read data DT, to the latch circuit LD. During the interval when the data latch clock signal ACT2 is asserted, that is, during the interval when the clock CLK is at low level and the address select signal ROMCS is at high level (the interval from time t2 to time t3), the latch circuit LD latches the signal VDATA.
In order to output the data read onto the bit line BL during the interval from t2 to t3 onto the data bus DBUS, the output enable signal OE and the read control signal CSRD are asserted (driven to the high level) at time t3. Thus, the output signal LDT of the latch circuit LD is output onto the data bus DBUS through the buffer 260.
Next, a leakage test of the flash memory configured as described above will be described with reference to FIG. 3B, which is a timing diagram of signals in the leakage test operation.
The operation at the leakage test mode is basically the same as the aforementioned operation at the data read mode. At the leakage test operation, the word line WL0 is set to be non-selected. A decision is made as to the presence or absence of leakage, depending on whether the potential on the precharged bit line BL keeps or falls below the precharge level. In FIG. 3B, broken lines indicate waveforms in the presence of leakage in the bit line. That is, the presence of leakage results in the inversion of an original signal being output onto the data bus DBUS, thereby allowing the presence of leakage to be found. In this case, it is required to set the frequency of the clock CLK low enough to allow the bit line potential to fall through leakage.
With the conventional flash memory described above, however, a delay of the data latch clock signal ACT2 may result in abnormal data being output. That is, the address select signal ROMCS suffers some delay because it is produced by decoding the address signals A18 to A2. As shown in FIG. 3A as well, therefore, the address select signal ROMCS may rise xcex94t1 behind time t1 and fall xcex94t2 behind time t3. During the interval from t3 to t3+xcex94t2, the precharge signal PRCV is asserted (driven to the low level) because the clock CLK is high and the address select signal ROMCS is high. For this reason, the bit line BL is also precharged during the interval of xcex94t2 immediately after time t3. In such a situation, if the falling of the data latch clock signal ACT2 is delayed, that is, if the signal ACT2 falls with a delay of xcex94t3 from time t3 in FIG. 3A, data on the bit line BL precharged during the interval of xcex94t2 will also be latched by the latch circuit LD. As a result, not only original data read onto the bit line BL during the interval from t2 to t3 but also false data precharged during the interval from t3 to t3+xcex94t3 may be output onto the data bus DBUS.
With the conventional flash memory, the power consumption tends to increase because the sense amplifier S/A is enabled all the time. As described previously, the sense amplifier S/A is always placed in the enabled state by the control signal PSV. Since the sense amplifier is enabled, for example, for a bit line precharge interval during which time it does not need to be enabled, the power consumption of the flash memory increases.
Moreover, the conventional flash memory may require a very long time for a leakage test. In the first place, the leakage current is a very low current. Thus, it takes a very long time for the bit line potential to fall enough through leakage. For this reason, it is required to set the frequency of the clock CLK sufficiently low at the leakage test operation. However, the clock CLK is not used for the flash memory only but used to control the operation of the entire microcomputer system. Therefore, changing the clock frequency only for the purpose of a leakage test of the flash memory is very troublesome and may result in a long test time.
A semiconductor memory device according to an aspect of the present invention comprises: a memory cell array having an array of a plurality of memory cells;
a read control circuit which produces a precharging signal to precharge a bit line of the memory cell array;
a row decoder which selects a word line of the memory cell array;
a column decoder which selects the bit line of the memory cell array;
a sense amplifier which amplifies data read from a memory cell selected by the row decoder and the column decoder to the bit line; and
a sense amplifier control circuit which is responsive to the precharging signal to control the sense amplifier, in reading data from a memory cell, the sense amplifier control circuit enabling the sense amplifier and inhibiting entry of read data from the memory cell into the sense amplifier only for a fixed interval after a fixed time after the precharging signal has been negated and allowing entry of the read data into the sense amplifier while the sense amplifier is being disabled.